In a Thin Film Transistor Liquid Crystal Display, generally, gates of individual Thin Film Transistors (TFTs) in a pixel area are supplied with gate driving signals by a gate driving apparatus. The gate driving apparatus can be formed on an array substrate of a Liquid Crystal Display with an array process, and such an integrated process can save the cost and also achieve a perfect appearance design of Liquid Crystal Panel with two sides thereof being symmetric. At the same time, the integrated process can omit a Bonding area and a Fan-out wiring space for the Integrated Gate Line Driving Circuit, and thus it can achieve a design of a narrow frame; moreover, said integrated process can also omit the Bonding process applied in the direction of gate lines, thus improving productivity and yield rate.
FIG. 1 shows a circuit diagram of one of shift registers constituting an integrated gate line driving circuit in the prior art; as shown in FIG. 1 the shift register includes four Thin Film Transistors T101, T102, T103 and T104 as well as a capacitor C102. FIG. 2 shows a timing sequence diagram of signals at inputs and outputs of the shift register shown in FIG. 1. The operating principle of the shift register can be described as follows: during the first phase, an input signal at a signal input terminal (INPUT) of the shift register is at a high level, and an input signal at a reset signal terminal (RESETIN) is at a low level, and thus T103 is switched on and T104 is switched off, a node PU is charged to a high level via T103; during the second phase, the input signal at the signal input terminal (INPUT) of the shift register is at a low level, the input signal at the reset signal terminal (RESETIN) is at a low level, and an input signal at a clock signal terminal (CLKIN) of the shift register is at a high level, and thus T101 is switched on, and a signal output terminal (OUTPUT) of the shift register is at a high level; moreover, since the input signal at the reset signal terminal (RESETIN) is at a low level, T102 and T104 are switched off; at this point, the node PU is in a floating state, and the level at the node PU continues to rise on the basis of the level during the first phase after coupling to the node PU via C102; during the third phase, the input signal at the signal input terminal (INPUT) of the shift register is at a low level, the input signal at the reset signal terminal (RESETIN) is at a high level, and thus T102 and T104 are switched on; as the sources of T102 and T104 are connected to a low level signal terminal (VSSIN), the signal output terminal (OUTPUT) and the node PU are at a low level; during the fourth phase, the input signal at the signal input terminal (INPUT) is at a low level, the input signal at the reset signal terminal (RESETIN) is at a low level, and thus T101, T102, T103 and T104 are switched off, the node PU is at a low level, and the signal output terminal (OUTPUT) remains at a low level; and during the fifth phase, the input signal at the signal input terminal (INPUT) is at a low level, the input signal at the reset signal terminal (RESETIN) is at a low level, all the transistors remain the state during the fourth phase, and thus the signal output terminal (OUTPUT) is still at a low level.
It can be seen that in a case of all of the signal input terminal (INPUT), the reset signal terminal (RESETIN) and the signal output terminal (OUTPUT) being at a low level, the clock signal terminal (CLKIN) is coupled to the node PU via a parasitic capacitance Cgd1 of T101 when it is at a high level so that the drain current of T101 increases, and thus the potential at the signal output terminal (OUTPUT) rises; moreover, since all of T103, T104 and T102 are switched off during the non-operating time, there is no pulling-down transistor to pull down the voltage at the signal output terminal (OUTPUT) when the potential at the signal output terminal (OUTPUT) rises due to the influence of the terminal CLKIN, thus bigger noise occurring in the signal output from the signal output terminal (OUTPUT).